Distributed Sensor Processing & Buffering

Connecting, bridging, managing, buffering and processing sensors with low power, small size FPGAs.

I/O Rich FPGAs - Lattice FPGAs offer multiple I/O banks, each capable of supporting independent voltage standards. Implement your bus expansion needs by using Lattice FPGA’s flexible I/Os.

Always-On Sensor Management - Enable that “Always-on” feature that you have been dreaming about by using Lattice’s low power, low cost FPGAs.

Distributed Heterogeneous Processing – With flexible I/Os, these small FPGAs can be placed around PCBs to enable direct connectivity to various sensors. Along with integrated DSPs, the same FPGAs can also provide sensor processing. Finally with additional integrated memory, the captured data can also be buffered prior to being sent to application processors. Together, these three blocks (flexible I/Os, integrated processing, and integrated memory) enable an optimized distributed heterogeneous processing (DHP) solution.

Jump to

Block Diagram

Always-On Sensor Management

  • Localized processing or pre-processing next to sensors for quick responsiveness
  • Improve layout by routing only a single interface to application processor by combining multiple sensors

I/O Hub

  • I/O rich FPGAs with support for various standards such as, but not limited to, I2C, SPI, UART, etc
  • Signal Aggregation to improve layout constraints caused by multiple signals
  • Flexible I/Os are able to be adjusted based on layout needs


  • Pedometer: Is your pedometer not power efficient? Lattice FPGAs enables your system to constantly monitor sensor activity while consuming very low power. Realize your Pedometer solution using Lattice FPGAs.
  • Context Awareness: Low power, low cost Lattice FPGAs can be used to create next generation context aware features in your device today.

Sensor Hub

  • Is the proliferation of sensors causing a I2C bus contention problem? Lattice FPGAs allow you to create dedicated I2C ports for those high bandwidth critical sensors.
  • Interface to the Application Processor using a lower power, higher bandwidth SPI interface
  • Poll sensors in low power while the Application Processor is in sleep mode. Enable customizable buffers, polling schemes based on your specific needs.

Design Resources for Sensor Management Solutions

Programmable Logic Reference Designs
  Provider iCE40 LP/HX/LM iCE40 Ultra / UltraLite iCE40 UltraPlus
Pedometer Reference Design Lattice  
Sensor Interfacing and Preprocessing Lattice
Touch Screen Controller Lattice    


Information Resources
Sensor Expansion in Mobile Handsets
SB002 10/18/2012
Sensor Expansion for Qualcomm MSM/QSD
SB001 10/18/2012
Radio Expansion in Portable Navigation Devices
SB005 10/18/2012
Sensor Mangement via MIPI SLIMbus
SB013 10/17/2012
Video Scaling and Expansion in Media Tablets
SB004 10/18/2012
Enabling 3D Active Shutter Glasses
SB007 10/18/2012
Enabling Wi-Fi Connectivity in Feature Phones
SB011 10/18/2012
Intelligent Sensor Management
SB003 10/17/2012
MIPI Battery Interface Using iCE40
I0224 4.0 10/26/2017
Low-Cost Docking Stations for Mobile Devices
SB009 10/19/2012
Common Analog Functions Using an iCE40 FPGA
SB012 10/17/2012
Enabling Dual SIM Phones
SB006 10/17/2012
Enabling the Nokia ECI for Smartphones
SB015 10/18/2012
Enabling Low-Cost Displays for Digital Still Cameras
SB014 10/18/2012
Consumer Solutions Brochure
I0222 6.0 10/24/2013
Enabling Dual Displays in Digital Still Cameras
SB010 10/19/2012
An FPGA Companion in Smartphone Design
1.0 5/1/2012
New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs
1.0 8/25/2013
Programmable Logic Devices in Mobile Handsets
1.0 6/1/2012
Programmable Logic Devices in Handsets (Chinese Language Version)
1.0 5/31/2012
The Industry Case for Distributed Heterogeneous Processing
WP0008 1.0 12/12/2016
iCE40 Ultra Wearables Infographic
1.0 12/31/2015


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