Tri-Speed Ethernet RGMII Reference Design

Implements 1G/100M Ethernet Application using TSE IP in RGMII mode with RISC-V MC Soft Processor

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This reference design demonstrates a 1G/100M Ethernet application using Lattice Triple-Speed Ethernet (TSE) IP Core in RGMII mode. The sample Ethernet packets are generated from RISC-V MC soft processor and transmitted to an on-board Ethernet PHY via the RGMII interface. The transmitted Ethernet packets are captured on a Personal Computer (PC) host and analyzed or observed using Wireshark software. This reference design also supports loopback mode to receive the transmitted Ethernet packets through RGMII RX interface back to RISC-V MC soft processor for data comparison.

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Feature

  • Interoperates with an on-board Ethernet PHY using RGMII interface
  • Supports operation speeds of 1 Gbps and 100 Mbps
  • Generates and compares Ethernet packets using the RISC-V MC soft processor
  • Configures the on-board Ethernet PHY using the RISC-V MC soft processor through the Management Data Input/Output (MDIO) interface
  • AHBL to AXI-Streaming data conversion block to support packets transaction between TSE IP and RISC-V MC

Block Diagram

Tri-speed Block DiagramExpand Image

Tri-Speed Ethernet RGMII Block Diagram

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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Tri-Speed Ethernet RGMII Reference Design – User Guide
FPGA-RD-02328 1.0 11/18/2025 PDF 1.3 MB
Tri-Speed Ethernet RGMII Reference Design - Source Code
1.0 11/18/2025 ZIP 24 MB

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