Arbitration and Switching Between Bus Masters

Reference Design LogoThis reference design provides a mode of connection and arbitration between multiple bus masters. While an I2C bus is used in this design, it is a generic implementation and the algorithm could be applied to any communication protocols. The I2C bus is chosen for its simple two-wire connection that reduces the board design complexity.


  • Multiple master arbitration, up to eight masters
  • Supports up to eight slave devices
  • 1:N switching between masters and slaves
  • I2C compatible master and slave devices

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Block Diagram

Arbitration and Switching between Bus Masters

Performance and Size

Tested Devices* Performance I/O Pins Design Size Revision
LCMXO2280C-5T100C >50 MHz 22 238 LUTs 1.1
LC4256ZE-5TN100C >50 MHz 22 189 Macrocells 1.1
LFXP2-5E-5M132C > 50 MHz 22 334 LUTs 1.1

1. The Max. Clock Frequency is obtained by running the Timing Analysis of Lattice design software. Please run the timing simulation after you merge it with your design.

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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Arbitration and Switching Between Bus Masters - Documentation
FPGA-RD-02104 1.2 1/21/2021 PDF 952.5 KB
Arbitration and Switching Between Bus Masters - Source code
RD1067 1.1 2/22/2010 ZIP 284 KB

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