SMBus Relay with filter (named I2C filter in this page) is designed to function as an invisible relay from the point of view of both Master and Slave devices on the bus. It is directly attached to the Master port and protect all Slave devices against malicious traffic generated from the Master port based on a whitelist of allowable commands set by the host (such as CPU, FPGA RoT design, and others).
The design is implemented in Verilog HDL. It can be configured and generated using the Lattice Propel™ Builder software. It can be implemented using the Lattice Radiant™ software and the Lattice Diamond® Place and Route tool.
Advanced High-performance Bus - Lite (AHB-Lite) interface - The module registers are accessed by the host (such as CPU, FPGA RoT design, and others) using a 32-bit AHB-Lite interface.
In compliance with SMBus protocol - Does not violate SMBus protocol and is transparent between the Primary and Secondary devices.
SMBus command – Verifies all the write access against a whitelist of allowable opcodes set inside the memory. Write is allowed if the bit value is 1 and not-allowed if the bit value is 0. 256 bits required to be supported for each Slave device.