SubLVDS to MIPI CSI-2 Image Sensor Bridge

Bridge industrial and A/V image sensors with SubLVDS interfaces to MIPI CSI-2 mobile app processors

Important: For new designs, Lattice recommends using the following modular IP blocks to implement this function:

The following Reference Design provides an integration example using these modular IP blocks

Most off-the-shelf Application Processors use industry standard interfaces such as MIPI CSI-2. However, several high-end image sensors traditionally focused on industrial and A/V markets have proprietary interfaces such as SubLVDS. The mobile industry accelerated many advances in application processor technology while additionally driving down cost and power. Many new applications want to leverage mobile innovations. At the same time the camera remains an extremely important feature in smartphones and tablets today.

Lattice CrossLink is a programmable video interface bridging device capable of converting Sony image sensors from SubLVDS to MIPI CSI-2 at up to 6 Gbps allowing for full resolution and bandwidth conversion. This bridge is available as free IP is available in Lattice Diamond for allowing easy configuration and setup.

Features

  • Supports 4, 8, or 10 data lanes from Sony image sensor in 10-bit or 12-bit pixel widths
  • Interfaces to MIPI CSI-2 Devices with 1 clock lane and 4 data lanes up to 6 Gbps total bandwidth
  • Generates XVS & XHS for image sensors in slave mode operation
  • Handles Sony IMX SubLVDS image sensors such as IMX236, IMX172, IMX178, IMX226, etc.
  • Easily configurable through Lattice Clarity Designer included in Lattice Diamond Software

Block Diagram

Camera interface conversion bridging: convert to/from MIPI CSI-2, SubLVDS, LVDS, CMOS, HiSPi and other sensor interfaces

Supported Configurations

Sony Sub-LVDS Input MIPI CSI-2 Output
4-lane, 10-bit RAW 4-lane, 10-bit RAW (RAW10)
4-lane, 12-bit RAW 4-lane, 12-bit RAW (RAW12)
6-lane, 10-bit RAW 4-lane, 12-bit RAW (RAW12)
6-lane, 12-bit RAW 4-lane, 12-bit RAW (RAW12)
8-lane, 10-bit RAW 4-lane, 10-bit RAW (RAW10)
8-lane, 12-bit RAW 4-lane, 12-bit RAW (RAW12)
10-lane, 10-bit RAW 4-lane, 10-bit RAW (RAW10)
10-lane, 12-bit RAW 4-lane, 12-bit RAW (RAW12)

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge
FPGA-IPUG-02006 1.4 5/10/2019 PDF 2 MB

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