iCE40 UltraPlus I2S IP

General purpose I2S controller

The Lattice Semiconductor general purpose I2S Controller offers an effective way to control an I2S bus. Additionally, it allows users to customize the I2S Controller to meet specific design requirements. The programmable nature of FPGAs provide users with the flexibility of configuring the I2S device to meet their needs.

I2S bus is a 3-wire, half-duplex serial link for connecting digital audio devices in an electronic system. The bus handles audio data and clocks separately to minimize jitter that may cause data distortion in the digital analog system.

The I2S bus only handles audio data, while the other signals, such as sub-coding and control, are transferred separately. To minimize the number of pins required and to keep wiring simple, a 3-line serial bus consisting of a line for two time-multiplexed data channels uses a word select line and a clock line.


  • Configurable as an I2S Transmit Master or I2S Receive Master
  • LMMI interface with LINTR interface
  • Configurable sample data resolution from 16 to 32 bits
  • Configurable data width from 16 to 32 bits
  • Active high interrupt output

Block Diagram

iCE40 UltraPlus I2S IP top Level Diagram


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I2S Controller IP Core
1.0 3/31/2018 IPK 127.7 KB
I2S Controller IP Core User Guide
1.0 2/21/2018 PDF 1.1 MB

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