Viterbi Decoder

Lattice's Viterbi Decoder is a parameterizable IP core with an efficient algorithm for decoding different combinations of convolutionally-encoded sequences. (Convolutional encoding is a process of adding redundancy to a signal stream in order to increase its robustness.) In the decoder, the convolutional coded sequences that have been corrupted by channel noise, are decoded back to the original sequence.

Many digital transmit-receive systems use a Viterbi decoder for decoding the convolutionally coded data. The digital data stream (e.g., voice, image or any packetized data) is first convolutionally encoded, modulated and transmitted through a wired or wireless channel. Noise from various sources is prone to enter into the channel. The data received from the channel at the receiver side is first demodulated and then decoded using the Viterbi decoder. By using both the original stream and the redundant stream, the Viterbi decoder core is able to correct for errors in the data caused by channel noise. The decoded output is equivalent to the transmitted digital data stream.

The decoder core supports various code rates, constraint lengths and generator polynomials. The core also supports soft-decision decoding and is capable of decoding punctured codes.

Features

  • Parameterizable Viterbi decoder
  • Available for ispXPGA and ORCA 4
  • Single clock synchronous design
  • Soft decision with parameterizable soft width
  • Non-punctured code rates of 1/2 and 1/3
  • Parallel or hybrid architecture implementation
  • Parameterizable constraint length from 3 to 8
  • Parameterizable convolution codes
  • Parameterizable traceback length
  • Internal depuncturing option
  • Puncturing rates from 2/3 to 12/13
  • Parameterizable puncture patterns for internal puncturing
  • Bit error rate monitore

Jump to

Block Diagram

Viterbi Decoder Block Diagram

Performance and Size

ORCA Series 4 FPGAs Performance and Resource Utilization1
Config # ORCA4
PFUs2
LUTs Registers External I/Os SysMEM EBRs fMAX (MHz) Latency
vterb_deco_o4_1_001.lpc 534 2104 997 10 8 71 174

1 Performance and utilization characteristics using ispLEVERTM software and targeting the or4e04, package BM416, speed 2.
2 Programmable Function Unit (PFU) is a standard logic block of Lattice devices. For more information, check the data sheet of the device.

ispXPGATM FPGAs Performance and Resource Utilization1
Config # XPGA
PFUs2
LUT-4s Registers External I/Os SysMEM EBRs fMAX (MHz) Latency
vterb_deco_xp_1_001.lpc 1020 2879 1422 10 16 72 174

1 Performance and utilization characteristics using ispLEVER software and targeting the LFX1200B, package FE680, speed grade 4.
2 Programmable Function Unit (PFU) is a standard logic block of Lattice devices. For more information, check the data sheet of the device.

Ordering Information

  • ordering Part Numbers:
    • For ORCA 4: VTERB-DECO-O4-N1
    • For ispXPGA: VTERB-DECO-XP-N1

To find out how to purchase the Viterbi Decoder IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
Downloads
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Viterbi Decoder User's Guide
11/1/2005 PDF 1016.7 KB
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IP Module Evaluation Tutorial
8/1/2004 PDF 216.1 KB
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Evaluation Package for Viterbi Decoder for ispXPGA
4/1/2003 ZIP 1.8 MB
Evaluation Package for Viterbi Decoder for ORCA 4
4/1/2003 ZIP 529.9 KB

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