DDR SDRAM Controller - Pipelined for ispXPGA & ORCA4


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DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to the regular SDRAM but doubles the bandwidth of the memory by transferring data twice per cycle on both edges of the clock signal, implementing burst mode data transfer.

The DDR SDRAM Controller is a parameterized core giving user the flexibility for modifying the data widths, burst transfer rates, and CAS latency settings of the design. In addition, the DDR core supports intelligent bank management, which is done by maintaining a database of "all banks activated" and the "rows activated" in each bank. With this information, the DDR SDRAM Controller decides if an active or pre-charge command is needed. This effectively reduces the latency of read/write commands issued to the DDR SDRAM.

Features

  • Performance of Greater than 100MHz (200 DDR)
  • Interfaces to JEDEC Standard DDR SDRAMs
  • Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits
  • Supports up to 8 External Memory Banks
  • Programmable Burst Lengths of 2, 4, or 8
  • Programmable CAS Latency of 1.5, 2.0, 2.5 or 3.0
  • Byte-level Writing Supported
  • Increased Throughput Using Command Pipelining and Bank Management
  • Supports Power-down and Self Refresh Modes
  • Automatic Initialization
  • Automatic Refresh During Nomal and Power-down Modes
  • Timing and Settings Parameters Implemented as Programmable Registers
  • Bus Interfaces to PCI Target, PowerPC and AMBA (AHB) Buses Available
  • Complete Synchronous Implementation

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Block Diagram

DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4 Block Diagram

Performance and Size

Performance and Resource Utilization for ORCA 41
Parameter File Core Configuration ORCA4 PFUs2 LUTs Registers Dist. RAM3 fMAX (MHz) External Pins
ddrct_gen_o4_1_008.lpc Generic I/F 344 1359 1559 N/A 100 (200 DDR) 239
ddrct_ahb_o4_1_008.lpc  AHB I/F 560 2322 2451 18 100 (200 DDR) 242
ddrct_pci_o4_1_008.lpc PCI I/F 510 2024 2070 16 664 246
ddrct_ppc_o4_1_008.lpc PPC I/F 492 1922 2170 18 100 (200 DDR) 181

1 Performance and utilization characteristics are generated using an OR4E022BA352 in ispLEVERTM v.3.0 software except for the AHB configuration 008 which is generated using OR4E042BM416. Synthesized using Synplicity Synplify, v.7.0.3. When using this IP core in a different density, package, speed, or grade within the ORCA Series 4 family, performance may vary slightly.
2 PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.
3 Dist. RAM = distributed memory.
4 Performance for the PCI configuration of this DDR core is limited by the maximum throughput of the PCI 2.2 interface (66MHz).
5 All parameters are set to their default values as shown in the Data Sheet.

Performance and Resource Utilization for XPGA1
Parameter File Device Core Configuration ispXPGA PFUs2 LUTs Registers fMAX (MHz) External Pins
ddrct_gen_xp_1_002.lpc LFX125B-4FH516CES/2X Generic I/F 393 1116 910 100 142
ddrct_ahb_xp_1_002.lpc LFX500B-4FH516CES/2X AHB I/F 751 1928 1599 100 145
ddrct_pci_xp_1_002.lpc LFX500C-4FH516CES/2X PCI I/F 688 1867 1333 663 170
ddrct_ppc_xp_1_002.lpc LFX500B-4FH516CES/2X PPC I/F 647 1670 1392 100 154

1 Performance and utilization characteristics are generated using the ispXPGA device shown above in ispLEVER v.3.1 software. The evaluation version of this IP core only works on this specific device density, package and speed grade. 2 PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.
3 Performance for the PCI configuration of this DDR core is limited by the maximum throughput of the PCI 2.2 interface (66MHz).

Ordering Information

  • Ordering Part Number For ORCA 4:
    • DDRCT-GEN-O4-N1
    • DDRCT-PPC-O4-N1
    • DDRCT-PCI-O4-N1
    • DDRCT-AHB-O4-N1
  • Ordering Part NumberFor ispXPGA:
    • DDRCT-GEN-XP-N1
    • DDRCT-PCI-XP-N1
    • DDRCT-AHB-XP-N1
    • DDRCT-PPC-XP-N1

To find out how to purchase the DDR SDRAM Controller - Pipelined IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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Board Timing Guidelines for the DDR SDRAM Controller IP Core
TN1071 1.1 9/6/2012 PDF 945.5 KB
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Board Timing Guidelines for the DDR SDRAM Controller IP Core
TN1071 1.1 9/6/2012 PDF 945.5 KB
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DDR SDRAM Controller User Guide
6/1/2004 PDF 1.1 MB
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IP Module Evaluation Tutorial
8/1/2004 PDF 216.1 KB
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Evaluation Package for DDR SDRAM Controller - Pipelined (AHB) for ispXPGA - Configuration 002
3/1/2004 ZIP 2 MB
Evaluation Package for DDR SDRAM Controller - Pipelined (Generic) for ispXPGA - Configuration 002
3/1/2004 ZIP 3 MB
Evaluation Package for DDR SDRAM Controller - Pipelined for ORCA 4 - PCI I/F Configuration 1
3/1/2004 ZIP 690.6 KB
Evaluation Package for DDR SDRAM Controller - Pipelined (PCI) for ispXPGA - Configuration 002
3/1/2004 ZIP 3.4 MB
Evaluation Package for DDR SDRAM Controller - Pipelined for ORCA 4 - AHB I/F Configuration 1
3/1/2004 ZIP 787.7 KB
Evaluation Package for DDR SDRAM Controller - Pipelined for ORCA 4 - GEN Configuration 1
3/1/2004 ZIP 1 MB
Evaluation Package for DDR SDRAM Controller - Pipelined (Power PC) for ispXPGA - Configuration 002
3/1/2004 ZIP 3.5 MB
Evaluation Package for DDR SDRAM Controller -Pipelined for ORCA 4 - PPC I/F Configuration 1
3/1/2004 ZIP 750.3 KB

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