The Lattice Finite Impulse Response (FIR) Filter IP Core is implemented using high performance sysDSP™ blocks available in Lattice devices. The input data, coefficient and output data widths are configurable over a wide range. The IP core uses full internal precision while allowing variable output precision with several choices for saturation and rounding. The coefficients of the filter can be specified at generation time and/or reloadable during run-time through input ports.
Highly configurable, multi-channel, and high-performance – The Lattice FIR (Finite Impulse Response) Filter IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices. In addition to single rate filters, the IP core also supports a range of polyphase decimation and interpolation filters. The utilization versus throughput trade-off can be controlled by specifying the multiplier multiplexing factor used for implementing the filter. The FIR Filter IP core supports as high as 256 channels, with each having up to 2048 taps.
Easily integrate FIR Filter into your design – This IP core reduces the effort required to integrate FIR Filters into developers’ FPGA designs. Using Clarity Designer or IPexpress tools in Lattice Diamond software, developers can easily configure and instantiate the IP core.