EP300: PowerPC Bus Arbiter

The EP300 PowerPC bus arbiter provides all the necessary functions to arbitrate multiple bus masters directly connected to the PowerPC host bus. The arbiter supports separate address and data bus tenure to realize the high performance allowed by the PowerPC bus architecture. Separate address bus grant and data bus grant signals are provided for each master device on the bus. The arbiter uses sophisticated built-in state machines to coordinate the address bus tenure and the data bus tenure. At any given cycle, up to two simultaneous bus accesses are allowed.

The EP300 PowerPC bus arbiter comes with the options of rotating priority or fixed priority schemes to meet the requirements for different system environments.


  • Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
  • Supports up to eight PowerPC bus masters with unlimited slave device support.
  • Supports two outstanding bus accesses.
  • Supports address only transfer and address bus retry.
  • Independent address bus and data bus tenure with separate bus grant and data bus grant.
  • Option for fixed priority assignment or rotating priority scheme.
  • Designed for ASIC or programmable logic device implementations in various system environments.
  • Fully static design with edge triggered flip-flops.
  • Optimized for ispXPGA product family.

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Block Diagram

Performance and Size

The following are typical performance and utilization results.

Lattice Device Utilization Performance
PFUs Slices LUTs Percentage
LFX1200B-4 17 98 41% 108Mhz
LFEC20 54 1% 133Mhz
LFXP10 54 1% 150Mhz
LFXP2-17E 54 1% 150Mhz

Ordering Information

This IP core is supported and sold by Eureka Technology, contact Eureka Technology at info@eurekatech.com or visit their website at www.eurekatech.com for more information.


Quick Reference
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PowerPC Bus Arbiter Datasheet
EP300 6/22/2007 PDF 91.9 KB

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