[Blog] A New Approach to Platform Management with Compute and FPGA

ASPEED’s management compute and Lattice’s low power programmability come together in a single device — the configuration modern platforms have been asking for.

Server architectures aren’t getting any simpler. AI workloads keep pushing platforms toward disaggregation, modular I/O, and faster iteration cycles — and OEMs and ODMs are being asked to deliver all of that while platforms keep evolving after they ship. The new ASPEED AST1840 brings two leading technologies together in a single device to meet that moment.

The AST1840 pairs ASPEED’s proven satellite management controller (SMC) with Lattice’s low power FPGA and integrates Caliptra-based Root of Trust (RoT) alongside them for OCP-aligned trust flows. It’s the configuration modern platforms have been asking for, and the AST1840 is the first device to deliver it.

What the AST1840 Delivers
Inside the AST1840, two technology streams sit side by side. ASPEED contributes the management compute core: an Arm Cortex-M4 running at 400 MHz with 4 MB of internal Flash, 16 MB of RAM and open-source RTOS Zephyr SDK. Lattice contributes a 25k LUT FPGA with 200 dedicated I/O pins, programmed in the Lattice Diamond® software toolchain familiar to FPGA developers. Alongside these two technology blocks, the device brings Caliptra-based hardware-rooted trust and physical anti-tamper.

AST1840 utilizes the LTPI interface to connect with and extend the management capabilities of the BMC. It supports the OBMF-ICP standard protocol defined by the Open Compute Project (OCP) via downstream and upstream dual USB interfaces, as well as the Streaming Boot functionality based on the Caliptra 2.x Root of Trust, helping teams align with evolving standards while enabling differentiated system designs.

Technical Specifications at a Glance

Built for Platform Evolution
The modern platform challenge is well understood: deliver designs that can be upgraded in the field, support an expanding set of management interfaces, and accommodate new standards and platform variants without starting over each time. The AST1840 addresses this challenge by combining the two capabilities customers need most, strong management compute and programmable logic, in a single device.

• A strong, proven management compute baseline. ASPEED’s Cortex-M4 with 4 MB of Flash, 16 MB of RAM and various interfaces carries the steady-state management workload across the product family.
• Scalability across the platform family. The integrated Lattice FPGA absorbs variant-specific differences between sled types, chassis revisions, and accelerator configurations.
• Flexibility for evolving platforms. With 25k LUTs and 200 dedicated I/O pins on board, the Lattice FPGA lets platforms reconfigure sideband, telemetry, and sensor interfaces as designs evolve.
• Faster time to market. Two device strengths in one, management compute and programmable logic, allow platform teams to iterate in the Lattice Diamond toolchain alongside their firmware development, compressing the cycle between platform changes and production silicon.
• Open-standard alignment. Native support for LTPI at 1 Gbps, OBMF-ICP over USB, and OCP Streaming Boot keeps designs aligned with where the datacenter ecosystem is heading.
• Smaller, denser management subsystems. Bringing a FPGA into a 17x17 mm satellite management controller (SMC) allows platform teams to plan for tighter, more compact management footprints as system densities increase.

AST1840 Deployment Scenarios

Hyperscale and AI Datacenter Platforms
AI buildouts are stretching what “management” means: more sideband signals, more power and thermal telemetry, more diverse accelerator boards under a single BMC. The AST1840 is well-suited to that environment — ASPEED’s management compute carries the steady-state workload, while the Lattice FPGA makes it practical to adapt the same controller across compute, storage, and accelerator sleds inside one platform family.

Modular and Disaggregated Servers
OCP-style disaggregated designs lean on satellite management controllers that handle local management while the BMC oversees the system. The AST1840 represents a new class of device for that role — a satellite management controller in which management compute and programmable fabric live together. It’s a class designed to grow, with both companies expected to keep building on the pattern as the ecosystem evolves.

LTPI at 1 Gbps gives the central BMC a clean pipe to the sled, OCP Streaming Boot supports modern provisioning flows, and the Lattice FPGA carries the platform-specific control and aggregation logic each design needs.

Enterprise Server OEM/ODM Designs
For OEMs and ODMs building general-purpose servers, the value is in adaptability and physical footprint. ASPEED’s management compute provides a stable baseline across product lines; the Lattice FPGA gives engineering teams the headroom to evolve I/O, sideband, and aggregation behavior late in the design cycle and after ship. As management subsystems push toward denser, smaller-footprint implementations, the AST1840 fits naturally.

Hardware-Rooted Trust for OCP Platforms
The AST1840’s Caliptra 2.x-based hardware-rooted trust aligns with the direction OCP RoTM (Root of Trust of Measurement) use cases are heading. For platforms targeting OCP-aligned trust flows — secure boot, attestation, and platform integrity — the AST1840 brings that capability into the same device as the management compute and the programmable logic.

Establishing the Next Platform Standard
The AST1840 is the first product from the ASPEED and Lattice collaboration, defining a new class of satellite management controller where management compute and FPGA are integrated in a single device. Future joint designs from the two companies are expected to extend this approach, building on a common foundation as customer platforms evolve.

The message is straightforward: the platforms you’re designing today will continue to evolve, and the AST1840 is designed to evolve with them, with ASPEED’s management compute providing the dependable baseline and Lattice’s FPGA delivering headroom for change.

Learn More
For technical deep-dives, evaluation kits, or to start sizing the AST1840 into your next platform, reach out to your ASPEED or Lattice account team. Joint applications-engineering support is available for sled-level and chassis-level designs.

Forward-Looking Statement
This blog contains forward-looking statements, including statements regarding the expected benefits, objectives, and future activities of the commercial relationship between Lattice and ASPEED Technology. These statements are based on current expectations, assumptions, and beliefs and are subject to risks and uncertainties that could cause actual results or outcomes to differ materially. Factors that could cause such differences include, among others, changes in market conditions, customer demand, competitive dynamics (including the evolving relationship between the parties), product development timelines, and the ability of the parties to execute on their respective strategies.

This blog describes a commercial relationship and does not create a legal partnership, joint venture, or similar arrangement between the parties.

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