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[Blog] Empowering FPGA-based Processor Design with Lattice Propel

[Blog] Empowering FPGA-based Processor Design with Lattice Propel
Posted 06/28/2024 by Mahj Leoparte, Product Marketing Manager at Lattice Semiconductor

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In the world of FPGAs, design software plays a crucial role in the overall system development process, making end-to-end programming easier with advanced features to enable design flexibility while fully utilizing the device capabilities.

However, oftentimes, non-FPGA designers or first-time users can experience a steep learning curve as FPGA-based System-on-chip (SoC) design is a multidisciplinary undertaking, requiring expertise in hardware architecture, embedded software, system integration, and more.

Lattice Propel™, a state-of-the-art graphical user interface (GUI)-based design environment, is designed to address these challenges by offering a complete set of graphical and command-line tools to create, analyze, compile, and debug both the hardware design of an FPGA-based system and the software design.

The latest version of Lattice Propel (2024.1) features updates that further simplify the development lifecycle and improve the hardware and software designer experience. Read on to learn how the latest updates can help you build FPGA-based processor systems in minutes.

A Critical Tool of Empowerment

The latest Lattice Propel offers enhanced ease-of-use by providing a user-friendly environment featuring drag-and-drop IP instantiation and a correct-by-construction design methodology. This allows designers to build complex systems quickly and efficiently with automated pin-to-pin connections, wizard-guided configuration, and parameterization to streamline the design process, enabling designers to integrate processors and peripheral IP rapidly.

Propel also drives flexibility through both graphical and command-line tools, catering to designers of all skill levels. It allows for script-level editing for granular control and updating existing designs. With a resource-rich environment, it is supported by a robust IP server that is regularly updated, allowing developers to implement new IP on Lattice FPGA-based designs in minutes.

Lastly, the tool’s Software Development Kit (SDK) offers a seamless software development environment with integrated industry-standard integrated development environments (IDE) and toolchain, software/hardware debugging capabilities, software libraries, and board support packages (BSP) for Propel-defined systems.

These features collectively contribute to a high-productivity design environment that can significantly reduce development time and complexity for embedded designers, allowing them to focus on innovation and optimization of their FPGA-based processor systems.

[Blog] Empowering FPGA-based Processor Design with Lattice Propel - Design Environment

Delivering Versatile Value Across Hardware and Software Environments

The newest version of Propel brings value to both hardware and software designers. It benefits IP partners and customers by providing a fully scripted flow for publishing IP for use within Propel and brings flexibility in the verification of systems via auto-generation of simulation scripts for designs containing mixed-language design blocks.

For embedded software designers, Propel can be used to analyze their C/C++ code for performance and ability to debug their code on a model of the system rather than needing a board. The addition of Quick EMUlator (QEMU) adds scalability across teams of software engineers, as each engineer can run their software code on the QEMU model without the need for multiple boards.

New, value-centric enhancements and features in Propel include:

  • QuestaSim Lattice Edition: A major step up in debug capabilities and improving design efficiency. Comparing to the previous version with ModelSim, QuestaSim shows better performance and faster simulation speed with more advanced simulation technology supporting multi-language development. This flow is semi-automatic and Propel handles most of the setup for users so they can get started easily.
  • Design creation enhancements (SoC in Builder & C/C++ in (SDK): Propel allows designers to get a head start in their design flow, offering several different templates for various application needs. Its new template creation flow enables users to see what templates are more easily available for creation. Designers can enhance productivity by creating custom C++ project templates that are sharable amongst cross-functional teams.
  • Design automation with Transaction Control Language (TCL): With Propel, designers can automatically generate a TCL build script that can be used to rebuild a design from scratch. This enables users who prefer to use a scripted, console-only design flow to get started very easily and continue development with Propel Builder.
  • Improved Design Rule Checking (DRCs): Propel Builder's DRC engine has also been enhanced in this release to support several new types of design rule checking. It now supports several new and enhanced DRCs, which enable users to develop their projects in new ways and improves their ease-of-use during their design flow by catching issues earlier on.
  • Color Customization Features: Color customization in Propel Builder has been greatly enhanced so that virtually everything in the GUI can be color customized. More color customization support has been added for component outline, component name, component ports, schematic background, GUI background, and console text.
  • Very High-Speed Integrated Circuit Hardware Description Language (VHDL) support: Designers can develop and import their own VHDL code, which can be directly integrated into their SoC designs in Propel Builder. Propel 2024.1 enhances its support to VHDL similar to Verilog. The RTL code written in VHDL, as well as Verilog, can be converted to glue-logic component for system integration.

[Blog] Empowering FPGA-based Processor Design with Lattice Propel - Complete your design

Streamlining FPGA Design Flows and Simulations

Propel now includes support for the QEMU virtual platform, enabling embedded designers to get started with Propel and Lattice's embedded design flows without requiring an actual device. This flow handles all the required toolchain and configuration setup for users, so they can easily get started simulating their own virtual RISC-V® design. QEMU is a versatile virtual platform that offers numerous benefits for users, particularly in the realms of software development & testing.

FreeRTOS upgrade: The Propel SDK also supports several new application templates to enable users to get started more easily with a variety of new design flows. In this release we have enabled two new FreeRTOS (Real-Time Operating System) based templates, which provide both complex and simple examples of how to get this running in your own RISC-V system. Additionally, we also support a new timing profiling template that demonstrates to users how they can generate their own performance data using gprof.

By harnessing the power of Lattice Propel, FPGA developers can unlock new possibilities quickly and more efficiently in their application and system development. Whether you’re a seasoned engineer or just starting out, Propel’s intuitive interface and comprehensive features will make it a game-changer to achieve success in minutes, from simple applications to complex embedded control and data processing systems.

To learn more about the latest version of Lattice Propel, please visit Lattice website and download your free license.