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Timing Critical Offload

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Legacy FPGA Designs can be Migrated to Achieve Better Performance

To illustrate the performance benefit of migrating to the new ASIC plarform, the fMAX results reported by the Spatan's static-timing-analysis report were compared to the results for rhe LaniceECP2. Given this parricular FIR-6lter design, a 117% performance gain was demonstrated over rhe…

Document

CertusPro-NX 10GbE PTP Mother Board - Quick Start Guide

QS074 V.2 Feb 2024 Doing More with the Lattice ORAN Timing and Synchronization Kit Check the Lattice website at www.latticesemi.com/oran-timing-synchronization-kit to download the full User’s Guide, the full source code of the default demo, and other resources.

Blog

FPGA design constraints - performance and analysis to achieve design and timing closure

Blog

The Importance of Timing Constraints in FPGA Designs

This blog post focuses on how to properly specify and validate timing constraints on a Lattice FPGA.

FAQ

Lattice ispLEVER: Timing Analysis: What is the I/O Timing Report?

Lattice ispLEVER: Timing Analysis: The I/O Timing Report (.ior) is a used to report the IO timing analysis of your design.  Input Setup and Hold times (Tsu, Th) and Clock-to-Output times (Tco) are reported. The IO Timing Report sweeps across all the speed grades to…

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Lattice ORAN Timing and Synchronization Kit

ORAN Sync Board has 2x 10GE & 2x 1GE ports, SMA & FMC connectors for testing, demos, development, GNSS & on-board timing sources, ToD, & PPS RJ48 connectors

FAQ

Timing: What is the I/O Timing Report?

Timing: The I/O Timing Report is a used to analyze the the IO timing in your design (Tsu, Th, Tco). The IO Timing Report sweeps across all the speed grades to determine the worst case.

FAQ

Diamond: What is Timing Simulation and what files does Lattice Diamond design generate to facilitate timing simulation.

Solution: The Timing Simulation (unlike Functional Simulation or Static Timing Analysis) is the closest emulation of a actually downloaded design to a device. A step ahead of functional simulation where only RTL code is required to verify the behavior,  the Timing Simulation…

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Making Timing Secure in 5G Open RAN Networks

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Lattice Expands ORAN Solution Stack with Precision Timing and Secure Synchronization Support for 5G+ Network Infrastructure

Lattice Semiconductor, the low power programmable leader, today expanded its Lattice ORAN™ solution stack to enable flexible, secure timing and synchronization for Open Radio Access Network (ORAN) deployments.

FAQ

Diamond:  Why is there a Timing Rule Check violation in the trace report on a ODDRX4B element for timing between the SCLK & ECLK inside this element?

This violation should not occur if the module is generated using IPExpress. If you are generating the module using IPExpress and continue to get this timing violation, check your preference file to make sure there is a FREQUENCY preference assigned on both the clocks going to the ECLK tree…

FAQ

CrossLink: What is the purpose of reset_n_i signal? Is there any input timing requirement for it?

In CrossLink IPs, reset_n_i is the asynchronous reset which is used in the design to reset the state machine, flipflops, logics to the initial state. There is no specific timing requirement because it is asynchronous reset so you can reset at any time.

FAQ

Radiant: Does Radiant perform static timing analysis (STA) on reset pins/signals?

Radiant performs static timing analysis (STA) on reset pin/signals that are using Local Set/Reset (LSR). To use LSR, user need to make sure that the GSR-related strategy settings are False/OFF (Force GSR on Synthesis and Infer GSR on MAP). User also need to make sure that they don't have any…

FAQ

Lattice Radiant: What does DOPAD_DEL on Timing analyzer report means?

The DOPAD_DEL is the delay from the PADDO port to the IOPAD signal switching rail to rail and measured at mid point. It is dependent on several factors such as :1. The drive strength : 8ma default2. The slew rate.Note: As #1 and #2 increases, the delay decreases.

FAQ

Lattice Diamond: Does Diamond timing analysis account for package flight time?

The timing data are measured on the IP boundary; that is, for pin-to-pin delays, that is the timing from the input port of the IP to the output port of the IP. This takes into account the load that the IP sees based on its connections. In the case of IO, there is an assumed 5 pF load…

FAQ

Lattice Radiant/Timing Analyzer: Is there a document describing how to use Radiant Timing Analyzer?

URL below is the Lattice Radiant Tutorial document. Navigate to page 38 for simple steps on how to use Radiant Timing Analyzer. https://www.latticesemi.com/view_document?document_id=53231 

FAQ

Whether STA(Static Timing Analysis) is supported on ispLSI1032 design within PrimeTime\uFF1F

No. STA(Static Timing Analysis) is not supported on ispLSI1032 design within PrimeTime. ispLSI1032 is an old CPLD and the timing on the CPLD is very simple. All paths between the logic blocks will have the same timing.

FAQ

What does "potential circuit loops found in timing analysis" in trace report mean?

Solution: The use of combinational loops has long been discouraged because this can cause significant stability and reliability problems in a design. The combinational loop behavior is usually dependent on the relative propagation delays of the loop's logic. Typically, combinational loops creep into…

FAQ

Lattice Radiant: What are the Timing constraints for PMI_FIFO_DC using EBR IMPLIMENTATION?

Here are the constraints to be used:set_max_delay -from [get_pins -hierarchical */*wp_sync1_r*.ff_inst/Q] -to [get_pins -hierarchical */*wp_sync2_r*.ff_inst/DF] 2set_max_delay -from [get_pins -hierarchical */*rp_sync1_r*.ff_inst/Q] -to [get_pins -hierarchical */*rp_sync2_r*.ff_inst/DF]…