The Serial Peripheral Interface (SPI) Flash Memory Controller IP Core provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device.
The controller has two separate ports: Data Port Advanced High-performance Bus (AHB-Lite) interface and Control Port Advanced Peripheral Bus (APB) interface.
Resource Utilization details are available in the IP Core User Guide.
Features
- Two bus interfaces: Data Port AHB-Lite Subordinate interface and Control Port APB Completer interface
- Option to individually configure the data bus widths of Data Port and Control Port to 8 or 32 bits
- Option to configure controller with Page Program Buffer to speed up Page Program
- Option to configure controller with Page Read Buffer to speed up Page Read
- Configurable serial clock (sclk_o) frequency
