The Lattice Semiconductor 25G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The 25GbE IP core consists of the 25-Gigabit Media Independent Interface (25GMII), which connects media access controllers (MACs) and Physical Layer devices (PHYs).
This IP Core is supported in the Lattice Avant-X FPGA for all available PCS and MAC options. These options are available in the Lattice Radiant™ software.
Resource Utilization details are available in the IP Core User Guide.
Features
MAC
- Compliant to the IEEE 802.3-2018 standard
- Supports standard 25 Gbps Ethernet link layer data rate
- 128-bit wide internal datapath operating at 195.3125 MHz
- AXI4-Stream interface on the client’s transmit and receive interfaces
PCS
- Designed to the IEEE 802.3-2018 25GBASE-R specification
- 64b/66b encoding and decoding
- 25GMII interface: 128-bit, 195.3125 MHz
- Supports AXI4-Lite interface for PHY and MAC register access
Example Design for the 25G Ethernet MAC + PHY IP Core validated on the Avant-X Versa Board is available on the IP Package and IP User Guide. To know more information about this example design, please refer to the latest IP User Guide.
