Why is there a limit on the number of 5V tolerant IOs in the ispMACH 4000 devices?
Background:
As the industry moves towards lower power and smaller process technologies, system and devices voltages go down. Several families of Lattice devices (such as the ispMACH 4000C/B/V and ispMACH 4000ZE) support 5V tolerant IOs to be backward compatible with the existing systems. For these device families, usually there is a limit on the number of 5V tolerant IOs as specified in the datasheet.
Explanation:
The limit comes from reliability analysis of FIT rate (failure rate) vs. area under stress at 5V on IO pins. Most of the new devices do not have 5V transistors but there is a max area that can sustain high voltage stress. In order to meet the target of FIT rate, Lattice puts the limit to guarantee the FIT rate for the life time of the device. If the limit of 5V tolerant IO is exceeded in an application, the system may be at risk of a higher failure rate that is no longer guaranteed by the Lattice specification.