Description:
- MACHXO3 device share the same SPI SysConfig ports for both SSPI and MSPI configuration mode.
- The Configuration(CFG) MSPI is designed to be bus friendly, i.e. when it's not actively booting, all MSPI pins are tri-stated.
- It's possible to allow another SPI host co-exist on the same bus. As long the another SPI host is bus friendly as well, i.e. external SPI host pins need to be to be tri-stated while MACHXO3 CFG MSPI is actively booting.
- Typically Lattice use DIP switch on the Evaluation board to select between SPI Masters.
Diamond Device Constraint Editor Software bundle both NV feature row setting and SRAM volatile fuse(User mode persistent) together in a single JEDEC file for MachXO3.
If you program the device internal flash with a JEDEC file which enabled both SSPI and MSPI port, it will enabled both hardware CFG MSPI/SSPI and user mode MSPI/SPI persistent bit where SPI ports will be unusable after entering user mode.
Solutions:
To enable CFG MSPI/SSPI without enabling user mode persistent bit, please follow below programming sequence:
- Program your desired JEDEC file to internal flash without enable the MSPI persistent bit - this also means that CFG sysConfig port is not enable
- Create a dummy JEDEC file then use the Diamond Programmer operation "FLASH Program Feature Rows" to write to feature row - with this method, you will not overwrite the internal flash bitstream, but able to setup CFG sysCOnfig port through write to feature row bit.
To enable dual boot from external flash through MSPI, follow below settings:
NV Feature Row Setting
- SLAVE_SPI_PORT=ENABLE
- MASTER_SPI_PORT=ENABLE
Diamond Device constraint setting
- SLAVE_SPI_PORT=ENABLE if you are using SPI background programing mode(Transfr), DISABLE if you are using normal SPI programing mode
- MASTER_SPI_PORT=DISABLE