MIPI CSI-2 / DSI D-PHY Receiver: What is the use of the RX_FIFO in the MIPI D-phy RX IP?
Description:
RX_FIFO is used when clk_byte_fr_i and clk_byte_o does not have the same frequency and/or is not synchronous, therefore it is used in order for the clocks to be synchronized and run at the same frequency. Nowfor the FIFO we introduce the The Packet delay that allows us to set a value in which when we would be reading from the FIFO, While depth is how much we can store in the FIFO. Setting the Packet Delay too high and having a depth of too low will cause an Overflow/Overrun, the reason for this is since in a FIFO we apply both Read and Write, whenever the Data is being written in the FIFO in a fast rate and the READ operation is delayed at a very long time, there will be a time that the FIFO will be Full, which will cause an Overrun/Overflow (which means Writing in a Full Fifo). Therefore, it is recommended that whenever we increase the packet delay, we also increase the Depth of the FIFO.Unfortunately there is no Flag to identify whether you have set the right FIFO Depth and Packet delay