CrossLink/CSI-2/DSI D-PHY Transmitter: When generating a CSI-2/DSI D-PHY transmitter version 1.1 from Lattice Diamond and simulating the generated test bench with Aldec I noticed that the synchronization sequence (0xB8) is not sent on all 4 MIPI lanes.The MIPI dphy seems to read the parallel data (signal dphy_pkt_i) only one clock cycle after dphy_pkten_i goes to 1 and not in the same clock as dphy_pkten_i goes to 1. Is this an error in the model of the MIPI dphy or does the MIPI dphy actually behave like this?
The dphy_pkt_i with 4 sets of 00_B8 as seen in the waveform is distributed among the data lanes. When enabling bypass packet formatter, data timing is 1 cycle off.