The MachXO2 device has an option to make dynamic update to the PLL.
Registers 0 through 11 are user accessible registers. The remaining registers are reserved for Lattice use or read-only access, and the user cannot write these.
For more information, refer to Table 17. EFB WISHBONE Locations for PLL Registers and the table note in TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide.
http://www.latticesemi.com/view_document?document_id=39080You can select other dividers and output frequency so that the DIVREF or DIVFBK is adjusted accordingly.
Yes, you can make changes in the parameters defined by defparam to change the clock frequency.
Yes, PLL has to be reset after the registers are configured, as can be seen from the code.