Article Details

ID: 3515
Case Type: faq
Category: Lattice IP/Reference Design
Related To: PCIe
Family: LatticeECP3

Search Answer Database

Search Text Image

How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe (Peripheral Component Interconnect Express) Endpoint IP core?

The Peripheral Component Interconnect Express (PCIe) endpoint IP we have currently can support only up to 8 Message Interconnect Express (MSI) interrupts.

This number of MSI interrupts available for the user can be checked in 'Multiple Message Capability' register of 'Message Control Register' of the PCIe Configuration space.