The source on the
website was fitted in previous ispLEVER Classic version 1.4. Because of the changes in ispLEVER Classic, the source cannot be directly fitted in latest ispLEVER Classic 1.6. To fit the design in this software, you can adjust constraints as follows:
- In Project Navigator, select any Verilog file in the left Sources in Project pane, then select Synplify Synthesize Verilog File in the right Processes for current source pane, then press the right mouse to open Properties dialog box for the process, set the following constraints:
- Map Logic to Macrocells = false
- Maximum Cell Fanin = 16
- Use Clock Period for Unconstrained I/O = false
- Open Optimization Constraints, and set the following constraints:
- Clock_enable_optimization = Auto
- Max_fanin = 32
- Max_pterm_collapse = 32
- Logic_fanin_limit = 32
- Logic_optimization_effort = 1
- Finally, you can run Fitter. This design can be fitted successfully.