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ID: 2692
Case Type: faq
Category: Debugging
Related To: Reveal
Family: All FPGA

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Reveal: How do I get further detail for the "Failed to read design" error message in Reveal Inserter?

When the design input is RTL, Reveal Inserter has to read or parse the design to provide the list of debug-able internal nodes.  If it encounters errors, Reveal Inserter simply reports "Failed to read design".  As Reveal Inserter uses the same parser as Generate Hierarchy, you can click on Design -> Generate Hierarchy in Lattice Diamond to get a list of errors found by the parser. Once the errors are resolved, you should be able to start Reveal Inserter.