For 7:1 LVDS design, it is usually used for unidirectional video data transfer. In Lattice's related reference designs -- RD1030/etc., data is driven to LVDS output pads through Output Buffer (OB) primitive
To temporarily shut down the LVDS output for power saving, replace the "OB" primitives with Output Buffer with Tristate (OBZ) primitives. Details of the "OBZ" primitive can be found in the FPGA Libraries Reference Guide at the
link.
To implement an output controlling function, modifications need to be made to the source code. Below is an example of the changes that need to be made:
For the Verilog version of RD1030, modifications need to be done in "tx_oddr_x2_mod.v":
replace
"OB buf_Q0_out_inst (.I(buf_Q0), .O(Q[0]));"
with
"OBZ buf_Q0_out_inst (.I(buf_Q0), .T(tri_state), .O(Q[0]));".
Here, you can drive "1" to "tri_state" when you want to drive tri-state to the 7:1 LVDS output pads.
Similar modifications need to be made in "tx_oddr_x2_mod.vhd" for the VHDL version of RD1030.