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ID: 2469
Case Type: faq
Category: Architecture
Related To: PLL/DLL/Clock Routing
Family: LatticeECP3

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Why does the PLL simulation model act differently than hardware?

A PLL is mainly an analog circuit. Because of this the PLL simulation model cannot operate in the same way as the hardware operates. The PLL simulation model also focuses on balancing a reasonable simulation time with actual hardware results.
For example, the PLL simulation will instantly lose lock and the output clocks will go low when a mismatch is found between the input clock and the reference clock. In hardware it will take some time for the PLL to lose lock and then to regain lock. Also in hardware the PLL output clocks will not go low. The output clock behavior will depend on what is happening with the reference and feedback clocks.