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ID: 1965
Case Type: faq
Category: Architecture
Related To: PLL/DLL/Clock Routing
Family: LatticeECP2/M

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What do users need to consider when using the LatticeECP2/M Dynamic Clock Select (DCS)?

Documentation on LatticeECP2/M's DCS is located in page 10-29 of the LatticeECP2/M SysClock PLL/DLL Design and Usage Guide. The link to the Application note(TN1103) can be located here.

One of the issues that users will run into when using the DCS is having too many clocks to the DCS. This results in an unroutable design. The description below explains the relationship between the number of clocks into the DCS and the number of DCS used.

In a LatticeECP2/M device a DCS can have its input come from either general purpose routing, another clock (via general purpose routing), or clock input I/O. There are a total of 8 available general purpose routing inputs to the 8 DCS in a LatticeECP2/M. As a result, there are only 8 unique sources that can go to the 8 DCS. However, each DCS can receive any two combination of the 8 inputs.

Another issue that users might encounter is unsuccessful switching between the two clock inputs into a DCS. Unsuccessful switching usually occurs when one of the input clocks is not running (i.e. stuck at logic HIGH or at logic LOW). For proper switching between the two clock inputs, both clock inputs must be running. This requirement is present because the DCS circuits uses the clock edges to do the proper switching. So, users will need to consider whether DCS is the proper clock multiplexer solution when at least one of the clock inputs is not a free running clock. An alternative solution for a non-free running clock is LUT-based clock multiplexer.

Users can also cascade DCS. However, this creates a long delay between the inputs of the first and last DCS' in the cascade. Users will need to take this into consideration (i.e. whether the long delay is acceptable). Note that to cascade DCS, some parts of the cascade connection use general purpose routing.