Article Details

ID: 1631
Case Type: faq
Category: Lattice IP/Reference Design
Related To: XAUI 10Gb Ethernet AUI
Family: All FPGA

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What conditions can lead to a loss of multi-channel alignment on the XAUI PCS IP?

The loss of multi-channel alignment (MCA) in the XAUI PCS IP can be caused by two types of factors:



  1. Any condition that can cause a burst of invalid 8b10b characters to the PCS/SERDES QUAD : 


    1. disturbing the SERDES inputs by physically breaking the line

    2. stopping the reference clock to the PCS/SERDES QUAD

    3. Corrupting data (invalid 8b10b characters).

  2. A condition that can prevent the /A/ channel alignment character  (K28.3) from simultaneously being  received on all four lanes for 4 consecutive times. This condition causes the MCA logic in the XAU PCS IP to lose alignment as shown in the IEEE 802.3ae specification PCS deskew State diagram.