Article Details

ID: 1501
Case Type: faq
Category: Device Programming
Related To: Configuration/Programming
Family: LatticeXP2

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Why does it take 4 minutes to program the XP2 FPGA device with the svf file generated by ispVM System software?

The official SVF standard does not support the looping and polling commands necessary to do a faster erase. In order to remain compatible with third party tools, we must use the worst case delay.


Our SVF interpreter supports looping and status polling, so the SVF file can be modified by hand to use these commands. If you do this, is will run much faster but won't be compatible with third party software.


For example:


RUNTEST             IDLE       3 TCK     2.40E+002 SEC;


Can be changed to:


LOOP 2400 ;


RUNTEST             IDLE       3 TCK     1.00E-001 SEC;


SDR        1              TDI  (0)


                               TDO  (1);


ENDLOOP ;


However, most 3rd-party vendors only support the SVF standard.


For customers who require 3rd-party support and fast erase and programming times, we recommend using STAPL instead of SVF. STAPL supports the looping and status polling algorithm.