Users can prevent Synplify from removing an input pin by setting the syn_force_pads synthesis attribute on the input port.
Below a Verilog example:
input myinput /* synthesis syn_force_pads=1 */;
Below a VHDL example:
attribute syn_force_pads: boolean;
attribute syn_force_pads of myinput : signal is true;
For more information, please refer to the Synplify Pro for Lattice Online Documents by selecting Help-> Online Documents from the Synplify Pro software.