LatticeSC SFI-5 Evaluation Board

This evaluation board provides a functional platform for development and rapid prototyping of applications that incorporate high-performance SFI-5 interfaces. It can also be used to verify compliance to the SFI-5 standard, as it interoperates with the LatticeSC SERDES channels capable of operating at data rates between 600 Mbps and 3.125 Gbps.

The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces. The board has several debugging and analyzing features for complete evaluation of the LatticeSC device.

Device Support

You will need the following software to use this board:

  • ispLEVER for design, fitting, place & route of Lattice programmable devices
  • ispVM to download your program to the LatticeSC or on-board Flash memory devices

SFI-5 Standard and Lattice Intellectual Property (IP) Core

The Lattice SFI-5 Intellectual Property (IP) core enables user instantiation of an OIF-compliant SERDES Framer Interface Level 5 (SFI-5) core in LatticeSC/M Field Programmable Gate Arrays (FPGAs). The SFI-5 defines a communications interface for a 40 Gbps optical link which typically consists of a Framer, FEC (Forward Error Correction) Processor, and SERDES. The purpose of the SFI-5 interface is to transmit data across multiple channels in parallel, where channels may incur different skews between the transmitter and receivers. The SFI-5 receiver delays the data received on all of the channels to match that channel which incurred the longest delay. This removes any skew variation between the channels.


  • LFSCM3GA80E-6FF1704C FPGA Device
  • SERDES/FPGA framer SFI-5 interface
  • 40-Gigabit SFI-5 interface via a 300-pin MSA transponder interconnection
  • SERDES high-speed interface SMA test points and clock connections
  • SERDES connections to RJ-45 connection for physical layer testing to CAT5 cable standards
  • 36-bit QDR2+ memory device
  • Power connections and power sources
  • ispVM® programming support
  • On-board and external reference clock sources
  • ORCAstra Demonstration Software interface via standard ispVM JTAG connection
  • User-defined input and output points
  • SMA connectors included for high-speed clock or data interfacing
  • Performance monitoring via Agilent Logic Analyzer probe connection

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Board Photos

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Ordering Information


Technical Resources
PCN14A-10 Notification of Coplanarity and height specification changes for the 1152-ball and 1704-ball organic flip chip BGA for the LatticeSC/SCM families of FPGAs - Japanese Lanauage
PCN14A-10 1 9/7/2010 PDF 462.4 KB
PCN14A-10 Notification of Coplanarity and height specification changes for the 1152-ball and 1704-ball organic flip chip BGA for the LatticeSC/SCM families of FPGAs
PCN14A-10 1 9/7/2010 PDF 339.7 KB

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