This evaluation board provides a functional platform for development and rapid prototyping of applications that incorporate high-performance SFI-5 interfaces. It can also be used to verify compliance to the SFI-5 standard, as it interoperates with the LatticeSC SERDES channels capable of operating at data rates between 600 Mbps and 3.125 Gbps.
The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces. The board has several debugging and analyzing features for complete evaluation of the LatticeSC device.
Device Support
You will need the following software to use this board:
- ispLEVER for design, fitting, place & route of Lattice programmable devices
- ispVM to download your program to the LatticeSC or on-board Flash memory devices
SFI-5 Standard and Lattice Intellectual Property (IP) Core
The Lattice SFI-5 Intellectual Property (IP) core enables user instantiation of an OIF-compliant SERDES Framer Interface Level 5 (SFI-5) core in LatticeSC/M Field Programmable Gate Arrays (FPGAs). The SFI-5 defines a communications interface for a 40 Gbps optical link which typically consists of a Framer, FEC (Forward Error Correction) Processor, and SERDES. The purpose of the SFI-5 interface is to transmit data across multiple channels in parallel, where channels may incur different skews between the transmitter and receivers. The SFI-5 receiver delays the data received on all of the channels to match that channel which incurred the longest delay. This removes any skew variation between the channels.