ispClock5312S Evaluation Board

The ispClock5312S Evaluation Board is a ready-made platform to help you evaluate and design with the ispClock5300 series of in-system-programmable zero delay universal fan-out buffers. The board includes an ispClock5312S in 48-pin TQFP package and a full set of features to help you use and evaluate the ispClock5312S. All user-programmable features of the ispClock5312S can be easily configured using Lattice Semiconductor's PAC-Designer® software.

Device Support

You will need the PAC-Designer software to use this board. PAC-Designer can be downloaded from the Lattice web site.

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Kit Contents

  • ispClock5312S Evaluation Board Featuring:
    • ispClock5312S in 48-pin TQFP package
    • SMA connectors for access to selected high-speed I/O
    • 8-bit configuration DIP switch
    • Flexible on-board I/O termination
    • Integrated power supply
  • ispDOWNLOAD Cable
  • AC Adapter
  • User Documentation

Board Photos

Top View

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Ordering Information

  • This product is no longer available for purchase.

  • The information provided here is for reference purposes only.
  • Reference number: PACCLK5312S-EVN
  • Contact your local Lattice sales representative for further information.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
ispClock5312S Evaluation Board User's Guide
Describes the features & functionality of the ispClock5312S Evaluation Board.
EB32 8/7/2007 PDF 739.9 KB

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