ispClock5312S Evaluation Board

Related Products

The ispClock5312S Evaluation Board is a ready-made platform to help you evaluate and design with the ispClock5300 series of in-system-programmable zero delay universal fan-out buffers. The board includes an ispClock5312S in 48-pin TQFP package and a full set of features to help you use and evaluate the ispClock5312S. All user-programmable features of the ispClock5312S can be easily configured using Lattice Semiconductor's PAC-Designer® software.

Device Support

You will need the PAC-Designer software to use this board. PAC-Designer can be downloaded from the Lattice web site.

Jump to

Kit Contents

  • ispClock5312S Evaluation Board Featuring:
    • ispClock5312S in 48-pin TQFP package
    • SMA connectors for access to selected high-speed I/O
    • 8-bit configuration DIP switch
    • Flexible on-board I/O termination
    • Integrated power supply
  • ispDOWNLOAD Cable
  • AC Adapter
  • User Documentation

Board Photos

ispClock5312S Evaluation Board Top ViewExpand Image

Top View

Click image to enlarge

Ordering Information

  • This product is no longer available for purchase.

  • The information provided here is for reference purposes only.
  • Reference number: PACCLK5312S-EVN
  • Contact your local Lattice sales representative for further information.

Documentation

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Support

Technical Support

Need Help? We're Here to Assist You

Licensing

Find The Software & IP Licenses You Need

Quality & Reliability

Reference Material to Help Answer Your Questions

Services

Outside Services to Help Get The Job Done

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.

会社情報

購入する

サポート
 
 
 
 
 
 
Lattice QR code