ispClock 5620 Evaluation Board / Development Kit

The ispClock Evaluation Board allows the designer to quickly configure and evaluate the ispClock5620 on a fully assembled printed-circuit board. The board features an ispPAC-CLK5620V-01T100C (20 outputs, 100-pin TQFP package), a header for user I/O, SMA connectors to selected high-speed I/O signals, LEDs for status indication, switches for added flexibility, and a JTAG interface for programming.

Device Support

You will need the PAC-Designer software (version 3.0 or later) to use this board. PAC-Designer can be downloaded from the Lattice web site.

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Kit Contents

  • ispClock Evaluation board
  • ispDOWNLOAD cable

Board Photos

Top View

Click image to enlarge

Ordering Information

  • Ordering Part number: PAC-SYSCLK5620AV
  • Click here to find an authorized Lattice distributor near you
  • Click here to order now from the Lattice Online Store

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
ispClock5620 Evaluation Board ispPAC-CLK5620-EV1
AN6064 11/1/2004 PDF 1019.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
ispClock5620 Evaluation Board ispPAC-CLK5620-EV1
AN6064 11/1/2004 PDF 1019.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Programming Cable User Guide
Describes the features and recommended usage guidelines of Lattice ispDOWNLOAD Cables.
FPGA-UG-02042 26.4 5/29/2020 PDF 1.4 MB

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