SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

Solve Mismatch between SubLVDS and ISP/AP using CSI-2 Interface

Many Image Signal Processors (ISP) or Application Processors (AP) use the Mobile Industry Processor Interface (MIPI®) Camera Serial Interface 2 (CSI-2) standard for image sensor inputs. However, some high-resolution CMOS image sensors use a proprietary SubLVDS output format.

Using the SubLVDS to MIPI CSI-2 Image Sensor Bridge reference design for CertusPro-NX™ devices solves the mismatch between SubLVDS output image sensor and an ISP/AP using CSI-2 interface.

RX and TX Permutations - Permutations apply to both RAW10 and RAW12. Pixel-to-Byte IP supports only 4 lanes on TX. To overcome these limitations, the different TX Gear setting is applied in D-PHY TX IP to handle 1 lane or 2 lane outputs, which require faster byte clock (hs_byte_clk = 2x).

Reference Clock Frequency - The appropriate value which can be obtained by pix_clk or GPLL output. This clock frequency must be 24 – 200 MHz.

Design and File Modification - This Reference Design is based on version 1.1.1 of the SubLVDS Image Sensor Receiver IP, version 1.3.0 of the Pixel-to-Byte Converter IP, and version 1.4.0 of the CSI-2/DSI D-PHY Transmitter IP.

Parameters and Port List - Can modify the directives according to your own configuration. The settings in the files must match SubLVDS RX IP, Byte-to-Pixel IP, and TX D-PHY IP settings created by Radiant.


  • Supports 4-, 6-, 8-, or 10-lane SubLVDS input to 1-, 2-, or 4-lane MIPI CSI-2 output
  • Supports input lane bandwidth of up to 1.25 Gbps and output lane bandwidth of up to 1.5 Gbps
  • Image cropping option
  • VSYNC and HSYNC can be generated to control sensor timing
  • Dynamic parameter setting through I2C
Lattice mVision Solutions Stack

Block Diagram

SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX Block Diagram


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