LatticeMico8 to WISHBONE Interface Adapter

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Reference Design LogoTo bridge the power and interoperability of both the LatticeMico8™ (LM8) 8-bit microcontroller and the WISHBONE bus interface, this reference design provides logic to adapt the LM8 external I/O to a WISHBONE master interface. The LM8 to WISHBONE adapter reference designer uses the upper address lines to decode each individual slave device. The number of address lines used for this is configurable, with the number of decoded slaves equaling 2N address lines used. Based on this address decoding, the desired device is enabled.

The LatticeMico8 is an open IP licensed core that is easily configured for FPGA/CPLD devices. This versatile microcontroller provides a wide range of capabilities with minimal device resources. The WISHBONE interface is a flexible, multipurpose general interface bus. With the increasing number of WISHBONE-capable open-source designs and intellectual property (IP), system design can be greatly simplified.

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Block Diagram

Performance and Size

Tested Devices* Performance I/O Pins Design Size Revision
LCMXO1200C-5FT256C N/A N/A 58 LUTs 1.1
LFXP2-5E-5QN208C >300 MHz 141 58 LUTs 1.1

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise. 

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeMico8 to WISHBONE Interface Adapter - Documentation
RD1043 1.1 2/23/2010 PDF 126.2 KB
LatticeMico8 to WISHBONE Interface Adapter - Source Code
RD1043 1.1 2/23/2010 ZIP 109.3 KB

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