HiGig/HiGig+ to SPI4 (X2S4) Bridging Solution

Related Products

Reference Design LogoThe XAUI/HiGig™/HiGig+™ to SPI4.2 (X2S4) bridge for LatticeSCM devices is the industry's lowest power programmable Fabric Interface Chip (FIC) solution. The solution, which utilizes the LatticeSCM's System Packet Interface Level 4 Phase 2 (SPI4.2) hard IP capability, and includes Lattice's 10Gb+ Ethernet Media Access Controller (MAC) soft IP core and the XAUI/HiGig/HiGig+ to SPI4.2 bridge design, provides a high-performance interface between the SERDES-based XAUI standard, used ubiquitously in 10Gb Ethernet networks, and SPI4.2, a very popular parallel bus interface used by Network Processor Unit (NPU) devices.

New 10 Gigabit Ethernet Service Cards are being implemented to support additional features and services. These cards are found in Metro Switches, Edge and Core Routers, Ethernet Backbone Switches, Aggregation Routers, Access Nodes, etc. The key functional silicon nodes on these cards are Ethernet Switches and Network Processors.

Shown below is an example of a 10Gb Ethernet Services card implementation using an Ethernet Switch device and a Network Processor. The physical interface to the Ethernet Switch devices is SERDES, supporting protocols like GE, SGMII, 2.5 GE/SGMII, XAUI, HiGiG, HiGig+. HiGig is a Broadcom proprietary interconnect scheme for the StrataXGS family. The HiGig protocol supports various switching functions like Quality-of-Service (QoS), link aggregation, etc. HiGig+ is a higher rate version of HiGig. The 10G NPUs typically have a SPI4.2 interface to link to the fabric. Hence, a Fabric Interface Chip (FIC) is required to bridge from the SPI4.2 on the NPU to the SERDES interface (GE/2.5GE/XAUI/HiGig/HiGig+) interface on the Ethernet Switch.

The LatticeSCM family with its industry-leading SERDES/PCS and built-in MACO (Masked Array for Cost Optimization) blocks implementing high performance, low power SPI4.2 interfaces, is a perfect fit for implementing these bridging solutions.

Competitive Advantages of the Lattice Offering

  • High Performance, low power (105mW typical at 3.125Gbps) SERDES that can also support the HiGig+ rate
  • The industry's lowest power SPI4.2 implemented in MACO at 0.85W, 50-80% lower than competition
  • The industry's smallest footprint solution (40% smaller than the competition) for a single configuration of the bridge when implemented in the LatticeSCM15 256-pin BGA package (17mm x 17mm)
  • A Lattice developed and supported solution. Competitor's solutions are from third-party IP vendors involving hefty NREs
  • Confidence from knowing the solution is fully Interoperable with major NPU and Ethernet switch vendors

Key Deliverables

  • XAUI to SPI4.2 Reference Design including required IP
  • User Guide
  • For HiGig/HiGig+ to SPI4.2 Reference Design including required IP, please contact your local Lattice sales office
  • Hardware Evaluation Platform: LatticeSC Communications Evaluation Board

Additional Licenses Requirements

  • LatticeSCM SPI4.2 MACO License (Free of charge)
  • LatticeSC/M 10Gb+ Ethernet MAC IP License (Part number: ETHER-10G-SC-U3)

For licenses and/or for HiGig support, please contact your local Lattice sales office.

Other Lattice FPGA Bridging Platforms

  • LatticeECP2M offers the industry's lowest cost SPI4.2 implementation together with integrated SERDES supporting commonly used protocols like GE, SGMII

For more details of the Lattice bridging solutions, please contact your local Lattice sales office.


  • Full-duplex bridging between NPUs (through SPI4.2) and Ethernet Switches (XAUI/HiGig/HiGig+)
  • XAUI standard datarate of 3.125Gbps on the SERDES as well as the HiGig+ data rate
  • Flow control in both directions
  • 32KBytes shared buffer for both Ingress and Egress directions
  • Minimum transmit burst sizes in increments of 16 bytes from 16 bytes up to 1008 bytes for optimized Network Processor applications
  • Marking of all error packets received before transmitting
  • Controllability and observability through a processor interface
  • Collection of statistics from the MAC

Jump to

Block Diagram

Performance and Size

Device Resource Utilization fMAX
Option Slices Registers EBRs
LFSCM15 XAUI 5245 6479 50 187.5
LFSCM15 HiGig+ 5295 6421 50 187.5


Technical Resources
Select All
XAUI to SPI4 (X2S) Bridge Reference Design plus Supporting IP
XAUI to SPI4 (X2S) Bridge Reference Design plus Supporting IP
RD1033 1.3 7/7/2008 ZIP 32.1 MB
XAUI to SPI4 (X2S) Bridge Reference Design plus Supporting IP v1.2
RD1033 01.2 6/1/2008 ZIP 32 MB
XAUI/HiGig/HiGig+ to SPI4 (X2S) Bridge Reference Design User Guide
RD1033 01.5 7/3/2008 PDF 586 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.