Flash memory has been widely used in embedded systems to support various functions in products like consumer electronics. How to effectively manage Flash memory and extend the service cycles of a Flash memory has become the challenge faced by designers.
The maximum number of erase cycles for each sector or block of Flash memory is close to 100,000. For most applications, a master device often accesses and updates a few specific sectors. These sectors can wear out in a short period of time while the rest of the sectors are still valid for applications. Such behavior significantly reduces the lifetime of Flash memory and impacts overall product cost. Wear leveling is a technique to extend the service cycles of Flash memory by averaging the number of accesses to each sector. As a result, the number of erase cycles is distributed among all the sectors, thus extending the life of each sector of the Flash memory.
This reference design implements the wear leveling control of data storage for SPI Flash memory. The CPU stores the number of erases, logic-map-physical table, and the valid page pointers into Embedded Block RAM (EBR) or User Flash Memory (UFM) to keep track of the SPI Flash memory usage. A WISHBONE bus is used to interface between the master device and the wear leveling controller.