Source synchronous interfaces consisting of multiple data bits and clocks have become a common method for moving image data within electronic systems. A prevalent standard is the 7:1 LVDS video interface (employed in Channel Link, Flat Link, and Camera Link), which has become a common standard in many electronic products including consumer devices, industrial control, medical, and automotive telematics. In many of these applications, the practice of using low-cost PLDs for image processing has become quite common.
The MachXO2, MachXO3 and ECP5 PLD families have been specifically engineered to support Display Interface (7:1 LVDS) video standard with built-in dedicated hardware interface blocks. This document describes the implementation methods and the advantages of using these devices for implementing this interface. By extension, support for Display Interface in these devices proves the feasibility of hardware implementation for all other LVDS source synchronous requirements as well.
Two designs are included in the discussion of this document. The first design is a simple loopback test that illustrates the use of the Display Interface transmitter and Display Interface receiver. The second design is an example that brings video data into the PLD through the Display Interface receiver, processes it and transmits it out via the Display Interface transmitter. Both designs are verified using the MachXO2 Control Evaluation Board.