SPI Peripheral

Reference Design LogoThis reference design implements a Serial Peripheral Interface (SPI) slave device interface that provides full-duplex, synchronous, serial communication with a SPI master. A simple back-end parallel interface provides the flexibility to interface with any system. This reference design instantly adds SPI bus capability to a device in an embedded system.


  • SPI slave with full-duplex capability
  • Supports 4-clock polarity and clock phase modes
  • Shares the SPI bus with other SPI slave devices
  • Receives and transmits registers configurable from 1 to 32 bits wide. Longer transfers can be done with software support
  • Double-buffered transmission allows new data to be written at the same time that previous data is being shifted out
  • Option for least-significant bit or most-significant bit first

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Block Diagram

Performance and Size

Tested Devices* Language Performance I/O Pins Design Size Revision
LCMXO640C-3T100C Verilog/VHDL >80 MHz 28 37 LUTs 1.1
LC4064ZE-4TN100C Verilog/VHDL >80 MHz 28 60 Macrocells 1.1
LPTM10-12107-3FTG208CES Verilog/VHDL >80 MHz 28 37 LUTs 1.1

1. The Max. Clock Frequency is obtained by running the Timing Analysis of Lattice design software. Please run the timing simulation after you merge it with your design.

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
Serial Peripheral Interface (SPI) - Documentation
RD1075 1.1 12/23/2011 PDF 158.7 KB
Serial Peripheral Interface (SPI) - Source Code
RD1075 1.1 12/23/2011 ZIP 124.8 KB

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