XIP5012C: RSA Signature Verification

Very compact IP core designed for RSA signature verification

XIP5012C supports all modulus lengths up to 4096 bits, and it can also be used for RSA public key exponentiation.

Easy integration with other FPGA logic, as the functionality of XIP4003C does not rely on any FPGA family specific features.


  • Minimal Resource Requirements: The entire XIP5012C requires 419 4LUTs (lookup tables) and 4 memory blocks (Lattice ECP5).
  • Performance: Despite its small size, XIP5012C can support more than 10 digital signature verification operations per second.
  • Standard Compliance: XIP5012C is compliant with FIPS 186-4.

Block Diagram

Internal high-level block diagram of XIP5012C

Resource Usage and Performance

FPGA family Resources Output bit rate
Lattice ECP5 419 4LUTs, 4 EBR 105.55 MHz

Resource usage and performance of XIP5012C on Lattice ECP5 FPGA family. On request, the resource estimates can also be supplied for other Lattice FPGA families.

Ordering Information

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP5012C can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

You can download the Lattice Product Brief from https://xiphera.com/partners/lattice/XIP5012C_PB_lattice.pdf


Information Resources
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Xiphera Lattice IP Core Metrics
1.0 8/5/2021 PDF 41.2 KB

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