I2C Slave IP Core

I2C Bus Interface

I2C (Inter-Integrated Circuit) bus is a simple, low-bandwidth, short-distance protocol. It is often seen in systems with peripheral devices that are accessed intermittently. It is commonly used in short-distance systems, where the number of traces on the board should be minimized. The device that initiates the transmission on the I2C bus is commonly known as the Master, while the device being addressed is called the Slave.

Lattice Semiconductor general-purpose I2C Slave IP Core provides device addressing, read/write operation and an acknowledgement mechanism. The programmable nature of FPGA provides users with the flexibility of configuring the I2C Slave device to any legal Slave address, thus, avoiding a potential Slave address collision on an I2C bus with multiple Slave devices.

It can be targeted to CrossLink-NX™ FPGA devices and implemented using the Lattice Radiant Software Place and Route tool integrated with the Synplify Pro® synthesis tool.


  • Supports 7-bit and 10-bit Addressing Mode
  • Supporting the bus speeds: Standard-mode (Sm) – up to 100 kbit/s, Fast-mode (Fm) – up to 400 kbit/s and Fast-mode Plus (Fm+) – up to 1 Mbit/s
  • Integrated Pull-up and Integrated Glitch filter
  • Polling and Out-of-band Interrupt Modes
  • Supports Clock stretching
  • Configurable ACK/NACK response on address and data phases

Block Diagram

I2C Slave IP Core Block Diagram


Quick Reference
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I2C Slave IP Core - Lattice Radiant Software
FPGA-IPUG-02072 1.4 5/31/2022 PDF 703.8 KB

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