DDR/DDR2 SDRAM Controller MACO Core


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IP ExpressThe DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that interfaces with industry standard DDR/DDR2 SDRAM devices and modules. This IP core is an IPexpress configurable core that provides the flexibility for modifying data widths, burst transfer rates, and CAS latency settings in a design. It provides a simple command interface for application logic. The controller can be configured to function as a DDR only or DDR2 memory controller.

MACOThis proven DDR/DDR2 core is optimized utilizing MACO ASIC gates in the LatticeSCM devices, resulting in fast, small cores that utilize the latest architecture to its fullest.

Note the RLDRAM IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.

Software Requirements

  • ispLEVER version 7.1 or later
  • MACO design kit
  • MACO license file

Features

  • Interfaces to industry standard DDR and DDR2 SDRAM
  • Programmable burst length of 4 or 8
  • Posted CAS functionality
  • ODT signal generation
  • Programmable CAS latency of 3 or higher
  • Intelligent bank management to minimize ACTIVE commands
  • Synchronous implementation
  • Command pipeline to maximize throughput
  • Supports SDRAM data path widths of 8, 16, 32, 40, 64 and 72 bits. Data width of 72 is supported in flip-chip or wire bond packages only with single-ended DQS. Maximum data width with differential mode DQS is 40 in wire bond packages.
  • Varying address widths for different memory devices
  • Programmable timing parameters
  • Internal core frequency and DDR-2 DRAM frequency of 333MHz with two chip selects used
  • Byte-level writing through data mask signals
  • Supports both true and complementary DQS during write (for a maximum of 40 data bits). During read, the complementary pin is unused.
  • Maximum of two chip selects (includes the capability for both chip selects to be de-selected to allow for other chip selects to be added via FPGA gates)
  • Supports PCB trace lengths of up to eight inches.

Jump to

Block Diagram

DDR SDRAM Controller MACO

Performance and Size

Results for LatticeSCM1
Configuration SLICEs LUTs REGs PIOs
Type Data Width RA / CA Width LatticeSCM Part Speed
DDR2 16 13 / 9 TYP (-6) 269 225 387 43
DDR2 32 13 / 9 TYP (-6) 422 321 629 63
DDR2 64 13 / 9 TYP (-6) 729 515 1113 103
DDR2 72 13 / 9 TYP (-7) 806 562 1234 113

1.Performance and utilization characteristics are generated using Lattice's ispLEVER® 7.1 software. When using this IP core with different software or in a different speed grade, performance may vary. Not all configurations will fit on smaller LatticeSCM devices. These results are from Synplify Pro v9.4L.

Ordering Information

To download this MACO IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.

Licensing

IP Version: 2.3.

All MACO IP is free of charge. However a license key is required to enable simulation and bitstream generation. Please contact your local Lattice Sales Office to obtain your MACO IP license key. 

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DDR/DDR2 SDRAM Controller MACO Core User Guide
IPUG46 01.8 5/5/2010 PDF 1.9 MB

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