Video Frame Buffer IP Core

Supports Dynamic Parameter Updating through a Parameter Bus

The Video Frame Buffer IP Core buffers video data in external memory to be displayed on output devices such as computer monitors, projectors, and others. The Video Frame Buffer IP Core supports image sizes up to 4K x 4K with YCbCr 4:2:2, 4:4:4 and RGB video formats. The IP supports dynamic parameter updating through the AXI4-Lite interface or native parameter bus interface, which can be configured to operate on a different clock from the IP.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Supports single color, YCbCr 4:2:2, YcbCr 4:4:4, and RGB video formats
  • Supports input and output resolutions of 64 × 64 to 4 k × 4 k pixels
  • Supports serial and parallel pixel processing
  • Supports frame rate conversion
  • Supports dynamic parameter update of frame size

Jump to

Block Diagram

Performance and Size

IP Configuration for Nexus Family

For LIFCL-40-9BG400I using Synplify Pro of Lattice Radiant software 2.1 or later.
Configuration Fmax (MHz)*
i_clk_i
Fmax (MHz)*
mem_clk_i
Fmax (MHz)*
o_clk_i
Registers LUTs EBRs
Default 200 178.795 171.321 1031 903 2
Parallel processing is Unchecked,
Others = Default
200 161.238 182.484 959 854 2
Video format is YCbCr4:4:4 or RGB,
Video frame width = 1024,
Video frame height = 768,
Others = Default
200 178.795 182.482 1154 1083 2
Video frame width = 1920,
Video frame height = 1080,
Others = Default
200 180.701 182.482 1077 944 2
For LFD2NX-40-9BG256I using Synplify Pro of Lattice Radiant software 2.1 or later.
Configuration Fmax (MHz)*
i_clk_i
Fmax (MHz)*
mem_clk_i
Fmax (MHz)*
o_clk_i
Registers LUTs EBRs
Default 200 178.795 171.321 1031 903 2
Parallel processing is Unchecked,
Others = Default
200 161.238 182.482 959 854 2
Video format is YCbCr4:4:4 or RGB,
Video frame width = 1024,
Video frame height = 768,
Others = Default
200 178.795 182.482 1154 1083 2
Video frame width = 1920,
Video frame height = 1080,
Others = Default
200 180.701 182.482 1077 944 2
For LFD2NX-40-9BG256I using Synplify Pro of Lattice Radiant software 2.1 or later.
Configuration Fmax (MHz)*
i_clk_i
Fmax (MHz)*
mem_clk_i
Fmax (MHz)*
o_clk_i
Registers LUTs EBRs
Default 200 178.795 171.321 1031 903 2
Parallel processing is Unchecked,
Others = Default
200 161.238 182.482 959 854 2
Video format is YCbCr4:4:4 or RGB,
Video frame width = 1024,
Video frame height = 768,
Others = Default
200 178.795 182.482 1154 1083 2
Video frame width = 1920,
Video frame height = 1080,
Others = Default
200 180.701 182.482 1077 944 2
For LAV-AT-G70-1LFG1156I device
Configuration Fmax (MHz)
i_clk_i
Fmax (MHz)
o_clk_i
Fmax (MHz)
mem_clk_i
Registers LUTs EBRs
Default 250 250 250 810 1228 0
Memory Interface = AXI4
Video Interface = UVSI
Dynamic = AXI4-Lite
Others = Default
250 250 250 1929 2548 2
Memory Interface = AXI4
Video Interface = UVSI
Dynamic = AXI4-Lite
FIFO Type = Distributed
Others = Default
200 250 250 1929 2548 0
For LFCPNX-100-7LFG672I device
Configuration Fmax (MHz)
i_clk_i
Fmax (MHz)
o_clk_i
Fmax (MHz)
mem_clk_i
Registers LUTs EBRs
Default 200 197 197 741 1073 0
Memory Interface = AXI4
Video Interface = UVSI
Dynamic = AXI4-Lite
Others = Default
200 194 199 1849 2429 2
Memory Interface = AXI4
Video Interface = UVSI
Dynamic = AXI4-Lite
FIFO Type = Distributed
Others = Default
200 194 199 1859 2429 0
For LN2-CT-20-1ASG410I device
Configuration Fmax (MHz)
i_clk_i
Fmax (MHz)
o_clk_i
Fmax (MHz)
mem_clk_i
Registers LUTs EBRs
Default 250 250 250 810 1228 0
Memory Interface = AXI4
Video Interface = UVSI
Dynamic = AXI4-Lite
Others = Default
250 250 250 1929 2548 2
Memory Interface = AXI4
Video Interface = UVSI
Dynamic = AXI4-Lite
FIFO Type = Distributed
Others = Default
200 250 250 1929 2548 0

*Note: Fmax is generated when the FPGA design only contains Video Frame Buffer IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

  Part Numbers
Device Family Multi-site Perpetual Single Seat Annual
Certus-N2 VFB-CN2-UT VFB-CN2-US
Avant-G VFB-AVG-UT VFB-AVG-US
Avant-X VFB-AVX-UT VFB-AVX-US
Avant-E VFB-AVE-UT VFB-AVE-US
CertusPro-NX VFB-CPNX-UT VFB-CPNX-US
CrossLink-NX VFB-CNX-UT VFB-CNX-US
Certus-NX VFB-CTNX-UT VFB-CTNX-US
ECP5 VFB-E5-UT -
LatticeECP3 VFB-E3-UT -
LatticeECP2 VFB-P2-UT -
LatticeECP2M VFB-PM-UT -
LatticeXP2 VFB-X2-UT -

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the Video Frame Buffer IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Video Frame Buffer IP User Guide
FPGA-IPUG-02137 1.4 12/20/2024 PDF 1.6 MB
Video Frame Buffer IP Core User's Guide
IPUG107 2.0 3/24/2015 PDF 2.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Video Frame Buffer IP Release Notes
FPGA-RN-02042 1.0 12/20/2024 PDF 195.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB

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