Video Frame Buffer IP Core

Supports Dynamic Parameter Updating through a Parameter Bus

Related Products

Related Applications


Newsletter Subscription
The Video Frame Buffer IP Core buffers video data in external memory to be displayed on output devices such as computer monitors, projectors, and others. The Video Frame Buffer IP Core supports image sizes up to 4K x 4K with YCbCr 4:2:2, 4:4:4 and RGB video formats. The IP supports dynamic parameter updating through the AXI4-Lite interface or native parameter bus interface, which can be configured to operate on a different clock from the IP. Simple frame rate conversion is employed to support different input and output frame rates.

Features

  • Supports single color, YCbCr 4:2:2, YcbCr 4:4:4, and RGB video formats
  • Supports input and output resolutions of 64 × 64 to 4 k × 4 k pixels
  • Supports serial and parallel pixel processing
  • Supports frame rate conversion
  • Supports dynamic parameter update of frame size

Jump to

Block Diagram

Video Frame BufferExpand Image

Ordering Information

The Video Frame Buffer IP is provided at no additional cost with the Lattice Radiant™ software.​

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Video Frame Buffer IP Core - User Guide
FPGA-IPUG-02137 1.6 12/11/2025 PDF 1.6 MB
Video Frame Buffer IP Core User's Guide
IPUG107 2.0 3/24/2015 PDF 2.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Video Frame Buffer IP Core - Release Notes
FPGA-RN-02042 1.2 12/11/2025 PDF 230.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW