DDR SDRAM Controller - Pipelined


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The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR SDRAM. The memory controller provides a generic command interface to the user's application. This interface reduces the effort to integrate the module with the remainder of the application and minimizes the need to deal with the DDR SDRAM command interface. The timing parameters for the memory can be set through the signals that are input to the core as part of the configuration interface. This enables switching between different memory devices and modification of timing parameters to suit the application using the same netlist.

Hardware Demo

A hardware demonstration bitstream for this IP core is available for use with the LatticeEC Advanced Evaluation Board. The bitstream, and a complete description of its operation is available for download by clicking the "Design Files" link in the resource box on this page.

Features

  • Interfaces to industry standard DDR SDRAM devices and modules
  • High-performance DDR 400/333/266/200/133 operation for LatticeECP3, LatticeECP2/M, LatticeECP2/MS and LatticeSC/M devices; DDR 333/266/200/133 operation for LatticeECP/EC devices; and DDR 266/200/133 operation for LatticeXP devices
  • Programmable burst lengths of 2, 4 or 8 for DDR
  • Programmable CAS latency of 2 or 3 cycles for DDR
  • Intelligent bank management to optimize performance by minimizing ACTIVE commands
  • Supports all JEDEC standard DDR commands
  • Two-stage command pipeline to improve throughput
  • Supports both registered and unbuffered DIMM
  • Command burst function with dynamic burst size control
  • Supports all common memory configurations
    • SDRAM data path widths of 8, 16, 24, 32, 40, 48, 56, 64 and 72 bits
    • Variable address widths for different memory devices
    • Up to eight (DDR) chip selects for multiple SO/DIMM support
    • Programmable memory timing parameters
    • Byte-level writing through data mask signals

The DDR SDRAM Controller - Pipelined is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

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Block Diagram

DDR SDRAM Controller Pipelined

Performance and Size

LatticeECP31
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 3-1 parameter defaults 1175 1403 1594 249 200MHz (400 DDR)

1. Performance and utilization characteristics are generated using LFE3-95E-8FN1156C with Lattice Diamond 1.1 software. Performance may vary when using this IP core in a different density, speed or grade within the LatticeECP3 family.
2. SDRAM data path width of 32 bits.

LatticeECP2M/S1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 3-1 parameter defaults 1195 1386 1558 249 200MHz (400 DDR)

1. Performance and utilization characteristics are generated usingLFECP2M-35E-7F672C with LatticeDiamond 1.1 software. Performance may vary when using this IP core in a different density, speed or grade within the LatticeECP2M/S family.
2. SDRAM data path width of 32 bits.

LatticeECP2/S1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 3-1 parameter defaults 1195 1386 1558 249 200 MHz (400 DDR)

1. Performance and utilization characteristics are generated using LFECP2-50E-7F672C with Lattice Diamond 1.1 software. Performance may vary when using this IP core in a different density, speed or grade within the LatticeECP2/S family.
2. SDRAM data path width of 32 bits.

LatticeEC/P1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 3-1 parameter defaults 1295 1367 1761 249 166 MHz (333 DDR)

1. Performance and utilization characteristics are generated using LFECP33-5F672C with Lattice Diamond 1.1 software. Performance may vary when using this IP core in a different density, speed or grade within the LatticeECP/EC family.
2. SDRAM data path width of 32 bits

LatticeSC/M1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 3-1 parameter defaults 1111 1277 1517 237 200 MHz (400 DDR)

1. Performance and utilization characteristics are generated using LFSC3GA25E-6F900C with Lattice Diamond 1.1 software. Performance may vary when using this IP core in a different density, speed or grade within the LatticeSC/M family.
2. SDRAM data path width of 32 bits.

MachXO21
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 3-1 parameter defaults 631 1184 1139 151 133 MHz (266 DDR)

1.Preliminary information. Performance and utilization characteristics are generated using LFXP2-17E-6F484C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the MachXO2 family, performance may vary.
2.SDRAM data path width of 16 bits.

LatticeXP21
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 3-1 parameter defaults 1193 1384 1558 249 200 MHz (400 DDR)

1. Performance and utilization characteristics are generated using LFXP2-17E-6F484C with LatticeDiamond 1.1 software. Performance may vary when using this IP core in a different density, speed or grade within the LatticeXP2 family.
2. SDRAM data path width of 32 bits.

LatticeXP1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 3-1 parameter defaults 1295 1367 1761 249 133 MHz (266 DDR)

1. Performance and utilization characteristics are generated using LFXP20E-5F484C with Lattice Diamond 1.1 software. Performance may vary when using this IP core in a different density, speed or grade within the LatticeXP family.
2. SDRAM data path width of 32 bits.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
MachXO2 DDRCTWB-M2-UT DDRCTWB-M2-US
LatticeECP3 DDRCT-GEN-E3-UT6 DDRCT-GEN-E3-US
LatticeECP2/S DDRCT-GEN-P2-UT6 -
LatticeECP2M/S DDRCT-GEN-PM-UT6 -
LatticeSC/M DDRCT-GEN-SC-UT6 -
LatticeXP2 DDRCT-GEN-X2-UT6 -
LatticeXP DDRCT-GEN-XM-UT6 -

IP Express Version: 6.10.

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DDR & DDR2 SDRAM Controller- Pipelined (MachXO2) IP Core User's Guide
ipug93 1.2 3/20/2015 PDF 3.5 MB
DDR/DDR2 SDRAM Controller - Pipelined User's Guide
Same manual for DDR1 and DDR2 cores. 		IPUG35 05.0 2/13/2012 PDF 3.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DDR Controller Evaluation Bitstream for LatticeEC Advanced Evaluation Board
Contains bitstream files (DDR) for use with the LatticeEC (and ECP) Advanced Evaluation Boards, along with a technical note description of the bitstream operation. 		6/1/2005 ZIP 13.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Evaluation Configuration for DDR SDRAM Conroller - Pipelined for ECP/EC and LatticeXP
10/1/2005 ZIP 631.2 KB
Evaluation Package for DDR SDRAM Controller - Pipelined for LatticeECP/EC
8/1/2006 ZIP 615.8 KB

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