The Controller Area Network (CAN) bus, originally developed for the car industry, is a fast, reliable and cost-effective data bus for multi-master and real-time applications.

The iniCAN core implements the low-level CAN protocol handling. The core contains the complete data link layer, including the framer, transmit and receive control, error handling, error reporting and bit synchronization. Simple message level transmit and receive interfaces facilitate smooth system integration. The core provides frame status, error counts and events as well as a low-level frame reference pointer which identifies the current bit position within a CAN frame. This feature comes in handy when developing CAN protocol analyzers or if detailed reporting on the bit-level is required.


  • Implementation of CAN protocol version 2.0A/B, ISO-118980-1
    • Supports standard and extended identifiers
  • Maximum bus speed of 1 Mbps
    • Programmable pre-scaler (1-256)
    • Programmable bit sampling settings according to CAN standard
  • Access to internal frame reference pointer
    • Indicates which bit of a CAN frame is currently on the bus
  • Built-in CAN error handling
    • Access to receive and transmit error counters
    • Bus state: Error active, error passive, bus-off
    • Interrupts for CRC error, bit stuffing error, bit error, format error, arbitration loss, and overload frame
  • Parallel message level interface
    • Simplifies system integration
  • Test modes
    • Listen only mode (controller doesn't send any messages to the bus)
    • Internal loop-back (controller receives only its own messages)
    • External loop-back (controller receives a copy of sent message)
  • Register based design
    • Technology independent
    • Full synchronous design
  • Supports CPU less operation


  • Transportation
  • Avionics and aerospace
  • Building automation
  • Machine control
  • Medical devices
  • Construction machines
  • Agriculture equipment

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Block Diagram

Performance and Size

The following are typical performance and utilization results.

Lattice Device Comb Seq Mem Performance Clock
iCE65L08-L 533 199 - 38 MHz
iCE65L08-T 533 199 - 17MHz
iCE40LP8K 561 199 - 28MHz
iCE40LX8K 561 199 - 29MHz

Ordering Information

This IP core is supported and sold by INICORE, contact INICORE at or visit their website at for more information.