DDR3 Memory Interface Demonstration

Core speed of 400 MHz and 800 Mbps Data Manipulation

The DDR3 Demo Design consists of two major parts: the DDR3 SDRAM Controller IP core and the User Logic block.

The DDR3 SDRAM Controller IP core interfaces directly with the onboard external DDR3 SDRAM to perform control, write, and read operations.

The User Logic block generates test data to be written to the SDRAM and compares the data read from the external DDR3 SDRAM to the expected result, flagging an error if a data mismatch is detected. The demo parameters can be modified using onboard DIP switches, whereas the status of the demo is indicated through the onboard LEDs.

This demo design demonstrates the functionality of the Lattice DDR3 SDRAM Controller IP operating at a core speed of 400 MHz and 800 Mbps using the Certus-NX Versa Evaluation Board and ECP5 VIP Processor Board.

Features

  • Generates 16/32-bit test data
  • Read and write to the onboard DDR3 SDRAM
  • This demo design allows you to:
    • Control certain parameters through DIP switches to modify demo test patterns
    • Initiate resets to the DDR3 SDRAM Controller and user logic
    • Observe critical signals through Reveal Analyzer

Block Diagrams

DDR3 Demo on Certus-NX Versa Evaluation Board

DDR3 Demo on ECP5 VIP Processor Board

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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DDR3 Demo on ECP5 VIP Processor Board- User Guide
FPGA-UG-02024 1.2 10/13/2022 PDF 1.9 MB
DDR3 Demo on Certus-NX Versa Evaluation Board - User Guide
FPGA-UG-02148 1.0 2/23/2022 PDF 1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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DDR3 Demo on Certus-NX Versa Evaluation Board - Bitstream
1.0 2/23/2022 BIT 792.5 KB
DDR3 Demo on ECP5 VIP Processor Board - Bitstream
10/13/2022 ZIP 105.3 KB

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