A SERDES recover clock(e.g. LatticeSC or LatticeECP3) is extracted from the incoming line data. Each Channel has it's own recovered clock. Even in a fully synchronous system, it does not have the same quality as the system reference clock. Recovered clock in general is used to capture and then hand off data to the FPGA side.
If the FPGA logic such as data generator (PRBS, counter, etc) or control logic are used for multiple channels or even multiple quads, it is not recommended to use one of the recovered clock from one channel to drive these general purpose data logic in the FPGA since the general FPGA logic are shared and used by multiple channels. It depends on the requirement of various applications, there are ways to improve the recover clock quality, such as using an external clock cleaner to recondition the recover clock.