Yes, but with the following limitation: the PLL VCO frequency must always remain within the fVCO usable frequency range for a given applied CLK input frequency.
For example, when using the LatticeXP2 device, the information in the datasheet (http://www.latticesemi.com/documents/DS1009.pdf) on page 3-27, states that the usable VCO frequency range is specified using the parameter fVCO:
PLL VCO Frequency = 435 MHz min, 870 MHz max
Note that the IPexpress PLL GUI states:
VCO frequency = CLKOP_frequency * CLKOP_divider_value
In this example, let's assume that the original PLL design resulted in a required 800 MHz VCO frequency for the applied reference CLK input frequency, and you now change the reference CLK input frequency to be 1.5 times higher. Doing this will make the new required VCO frequency be 1200 MHz for the same PLL counter divider settings which is outside the XP2's usable VCO frequency range, and as a consequence the PLL will probably lose lock.
In this case, if you need the input reference CLK frequency to cover a 1.5 X range and still have the PLL able to lock with the same PLL counter divider settings, then you will need to change the PLL divider settings such that the applied CLK frequency would never force the VCO to exceed it's usable frequency range given by the fVCO parameter in the device datasheet.
To correct this problem (if your design allows it), you could change the PLL dividers to give a lower initial VCO frequency down at maybe 500MHz so that the second 1.5 X higher VCO frequency would then be at 750MHz, and now both VCO frequencies will be within the fVCO usable VCO frequency range.
Note that if you do change the input clock frequency applied to the PLL, it may require up to the tLOCK (seconds), PLL Lock-in Time, to again lock to the new input frequency after applying a PLL reset and dynamic delay adjustment.