Description:
In VCS, an error can occur when simulating designs with some foundational IPs.
Solution:
This is due to the 'include lines in the Verilog files used for the IP/s. Thus, VCS cannot resolve these modules.
See the following steps to be able to run your VCS simulation (example design using PMI instantiation of memory):
1. Combine all your source files in a single .f file.
2. See the following example:
3. This will allow us to directly reference VCS to the correct file.
4. See the following VCS call with the .f file:
vcs -R -debug_access+all -timescale=1ps/1ps -sverilog +define+DEBUG=0 +define+SIMULATE +notimingchecks +libext+.v +define+functional +v2k \
+incdir+/tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/cae_library/simulation/verilog/lfmxo5/ \
+incdir+/tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/cae_library/simulation/verilog/uaplatform/ \
+incdir+/tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/ip/pmi/ \
+incdir+/*location of test.f*/ \
-y /tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/cae_library/simulation/verilog/lfmxo5/ \
-y /tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/cae_library/simulation/verilog/uaplatform/ \
-y /tools/dist/lattice/RADIANT/2023_1p.43.3/Linux/ip/pmi/ \
-f /*location of test.f*/test.f \
This should apply to other designs using IP/s if they use 'include lines to refer to other files.