Two PLLs get cascaded together, which is permitted in our application notes. But special care needs to be done in such design by the end users.
1. After power up or a reset, the PLL requires some time to wake up and obtain a LOCK state, at the same time the PLL is using its input and a feedback to perform system operation.
2. The second PLL also does the same thing at the same time. The problem is, it is using the clock output from the first PLL as its input to search for the LOCK. Since both PLLs are busy trying to obtain LOCK, with two dependent variables, the circuit has the potential to not obtain LOCK properly.
To resolve this potential issue: place the second PLL in a wait and reset state until the first PLL has obtained LOCK. You can use a delay circuit along with LOCK output to control the second PLL's reset signal.